Job Title: ASIC Design Manager
Degree Required: BS or Higher
Job Description:
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RTL Coding, including block design, top level design, Lower power design, CPF/UPF design
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Verify design and debug in RTL-level, gate-level and PG gate level
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Simulation, Design constraints, Coding Style checking, Cross clock domain checking, Synthesis and timing closure
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Bug analysis and fixing, formal check
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Area, Power, FIT estimation/measure, DFT related, ATE support
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Deliver design/verification/application documents/SPECs
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Work closely with algorithm engineers to develop/debug new IP/product
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Work closely with verification/system/Firmware engineers to verify/validate new IP/product
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Work closely with architecture and FW engineers to define function of blocks
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Work closely with architecture and FW to settle down SoC level, subsystem, block level FW/HW partition, architecture
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Be able to learn new knowledge
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Team culture and efficiency management, team output quality management, project planning, and schedule management
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Communication across teams
Job Requirements:
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Experience in Verilog code design and verification
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Experience in Unix/Linux OS, and scripting language like perl
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Experience in ASIC frontend flow and related tools (synthesis, formal, STA and DFT tools)
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Experience in Lower power design and verification with UPF/CPF
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Good understand on circuit design and timing constraint for synthesis/STA
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Familiar with C, UVM
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Familiar with formal check, DFT related, ATE related
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Strong problem-solving abilities
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Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form
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A high level of self-motivation, the ability to be a self-starter, with a good attitude and is highly responsible
- Good written and verbal communication skills and presentation skills
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Ability to work in a team environment
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Team management experience